In my fourth semester, I had a course called “Computer Architecture and Assembly Language.” As the name suggests, this course covered the details of assembly language and how the instruction set and the architectural design of the processor used, impacted each other.

MIPS (Microprocessor without Interlocked Pipeline Stages) Assembly language was used throughout to introduce various concepts, and assignments were given to code out in a SPIM environment.

For the end-of-the-semester project a Literature Review was required. It could be either software or hardware related but had to focus on computer architecture and how speed and optimized design was so important at every level.

This project was done in groups of two, and my partner and I decided to choose Network on Chip as the subject. We reviewed 250 research papers, going back to 2005, at their earliest. Of these, 50 papers were first shortlisted. This number was later cut down to 20 papers which were deemed as very relevant, finally 8 papers were selected for the actual review. Below you can find the abstract of the Literature Review that was submitted. For the full pdf version, please click here.

Abstract – The drawbacks of System on Chip, most importantly lack of scalability, have prompted new architectures, such as Network on chip (NoC) model, to come into being as a better alternative. Since first proposed, every year more and more new topologies and designs of NoC are presented in an effort to find the one with the best performance. In this paper, recent topologies that had been evaluated according to the chosen metrics of transport latency, energy dissipation and message throughput are compared and analyzed and the topologies with the best overall performance are highlighted.

Index Terms – Network on chip, topology, hybrid NoC, mesh, throughput, latency, energy.